module counter #
(
    parameter OUTPUT_WIDTH          = 8
)
(
    input                           clk,
    input                           rst,
    output reg[OUTPUT_WIDTH - 1:0]  cnt
);

    always @(posedge clk or negedge rst) begin
        if(rst) cnt <= 0;
        else cnt <= cnt + 1;
    end

endmodule  //counter